Senior FPGA Design Engineer
FPGA Design Engineer
FTE > Must be able to work 3 days per week in Cambridge, MASecurity Requirement:
Current in scope US Secret clearance STRONG preference will be given to candidates with in scope US TS clearance
We are seeking a talented senior engineer to join the digital design team. The successful candidate will contribute to FPGA development including architecture, design, synthesis, verification, validation, test and support. Candidate must have experience using high level design, simulation and verification tools and be familiar with process flows supporting design and verification for digital FPGA efforts. Applicant should also be familiar with embedded software development for FPGA SoCs.
Preference will be given to candidates with an understanding of hardware security, signal or image processing, filter design and algorithm implementation in hardware.
Direct experience with embedded FPGA design is required.
Required
Qualifications:
BSEE with 6
years relevant experience Fluent in Verilog/VHDL Understanding of networking layered models and protocols Implementation of FPGA functions to accelerate SW (checksum engines, packet parsing, etc.) Experience with Microchip Libero tools, PolarFire (SoC) devices, and IP Experience with joint design/debug with embedded software Experience debugging FPGA fabric designs with embedded processor software on HW Experience with design closure including timing, power and area for SWaP constrained designs Familiarity with high speed interfaces (10Gbit Ethernet, PCIe, DDR4, LVDS, etc) Experience with Linux and scripting languages Strong analysis and problem solving skills Minimum of 3 days onsite is required
Preferred
Qualifications:
MSEE with 6
years relevant experience Experience with 10GbitB Ethernet Experience with Matlab/Simulink Experience with Xilinx tools and devices Experience with implementation of image processing algorithms in firmwareEstimated Salary: $20 to $28 per hour based on qualifications.
FTE > Must be able to work 3 days per week in Cambridge, MASecurity Requirement:
Current in scope US Secret clearance STRONG preference will be given to candidates with in scope US TS clearance
We are seeking a talented senior engineer to join the digital design team. The successful candidate will contribute to FPGA development including architecture, design, synthesis, verification, validation, test and support. Candidate must have experience using high level design, simulation and verification tools and be familiar with process flows supporting design and verification for digital FPGA efforts. Applicant should also be familiar with embedded software development for FPGA SoCs.
Preference will be given to candidates with an understanding of hardware security, signal or image processing, filter design and algorithm implementation in hardware.
Direct experience with embedded FPGA design is required.
Required
Qualifications:
BSEE with 6
years relevant experience Fluent in Verilog/VHDL Understanding of networking layered models and protocols Implementation of FPGA functions to accelerate SW (checksum engines, packet parsing, etc.) Experience with Microchip Libero tools, PolarFire (SoC) devices, and IP Experience with joint design/debug with embedded software Experience debugging FPGA fabric designs with embedded processor software on HW Experience with design closure including timing, power and area for SWaP constrained designs Familiarity with high speed interfaces (10Gbit Ethernet, PCIe, DDR4, LVDS, etc) Experience with Linux and scripting languages Strong analysis and problem solving skills Minimum of 3 days onsite is required
Preferred
Qualifications:
MSEE with 6
years relevant experience Experience with 10GbitB Ethernet Experience with Matlab/Simulink Experience with Xilinx tools and devices Experience with implementation of image processing algorithms in firmwareEstimated Salary: $20 to $28 per hour based on qualifications.
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